1. Field of the Invention
The present invention relates to a data transmitting device, more particularly, to a data transmitting device capable of converting clock frequency by using a serializer such as data in order to match data with clock, and a flat plate display using the same.
2. Discussion of the Related Art
A flat plate display capable of displaying images by using digital data may include a liquid crystal display (LCD) using liquid crystal, a plasma display panel (PDP) using discharge of inactive gas, an organic light emitting diode (OLED) using organic light emitting diodes and the like.
Because of a trend of high resolution and large size required to display a high quality image, the amount of data transmission of such the flat plate panel display device has been increasing. As a result, the transmission frequency of data is getting high and the number of data transmission lines is increased such that electromagnetic interference (hereinafter, EMI) may occur a lot. The problem of EMI is generated in digital interface between a timing controller and a data driver of the flat plate display and it causes unstable driving of the device. To solve the problem of EMI and to reduce power consumption when data is transmitted at a high speed, the flat plate display uses data transmission methods that transmit data by using low voltage differential signals, wherein the data transmission methods includes an LVDS (Low Voltage Differential Signal) transmission method, a Mini-SVDS transmission method and the like. The interface between the timing controller and the data driver of the flat plate display typically uses the mini-LVDS data transmission method.
For the mini-LVDS data transmission, the timing controller includes an LVDS transmitter mounted in an output terminal and the data driver includes an LVDS receiver mounted in an input terminal. The LVDS transmitter converts data and a clock signal into low voltage differential signals and outputs the low voltage differential signals. The LVDS receiver converts the low voltage differential signals into the data and the clock signal.
The LVDS transmitter converts parallel data into high speed serial data and then converts the high speed serial data along with the clock signal into the low voltage differential signals to output the low voltage differential signals.
To match a timing transmitting the data with a timing transmitting the clock signal, the LVDS transmitter of the related art adjusts a delay time of the clock signal using a plurality of delay logic chains and buffers, thereby compensating a timing of the clock signal to minimize a time skew between the data and the clock signal.
The LVDS transmitter adjusts the clock timing using the logic buffers which separate from the serializer converting the parallel data into the high speed serial data. Because of that, the clock timing independently change without operating together the data according to the power, voltage and temperature changes, thereby skewing the predetermined timing skew between the data and the clock. If it is skewed the timing skew between the data and the clock, it is occurred an error that the LVDS receiver cannot restore accurate data.